Various types of packaged integrated circuits are known in the prior art. The following patents and published patent applications of the present inventor and the references cited therein are believed to represent the state of the art:
U.S. Pat. Nos. 4,551,629; 4,764,846; 4,794,092; 4,862,249; 4,984,358; 5,104,820; 5,126,286; 5,266,833; 5,546,654; 5,567,657; 5,612,570; 5,657,206; 5,661,087; 5,675,180; 5,703,400; 5,837,566; 5,849,623; 5,857,858; 5,859,475; 5,869,353; 5,888,884; 5,891,761; 5,900,674; 5,938,45; 5,985,695; 6,002,163; 6,046,410; 6,080,596; 6,092,280; 6,098,278; 6,124,637; 6,134,118.EP 490739 A1; JP 63-166710WO 85/02283; WO 89/04113; WO 95/19645
The disclosures in the following publications:
“Three Dimensional Hybrid Wafer Scale Integration Using the GE High Density Interconnect Technology” by R. J. Wojnarowski, R. A. Filliion, B. Gorowitz and R. Sala of General Electric Company, Corporate Research & Development, P.O. Box 8, Schenectady, N.Y. 12301, USA, International Conference on Wafer Scale Integration, 1993.
“M-DENSUS”, Dense-Pac Microsystems, Inc., Semiconductor International, December 1997, p. 50;
“Introduction to Cubic Memory, Inc.” Cubic Memory Incorporated, 27 Janis Way, Scotts Valley, Calif. 95066, USA;
“A Highly Integrated Memory Subsystem for the Smaller Wireless Devices” Intel(r) Stacked-CSP, Intel Corporation, January 2000;
“Product Construction Analysis (Stack CSP)”, Sung-Fei Wang, ASE, R & D Group, Taiwan, 1999;
“Four Semiconductor Manufacturers Agree to Unified Specifications for Stacked Chip Scale Packages”, Mitsubishi Semiconductors, Mitsubishi Electronics America, Inc., 1050 East Arques Avenue, Sunnyvale, Calif. 94086, USA;
“Assembly & Packaging, John Baliga, Technology News, Semiconductor International, December 1999;
“<6 mils Wafer Thickness Solution (DBG Technology)”, Sung-Fei Wang, ASE, R & D Group, Taiwan, 1999;
“Memory Modules Increase Density”, DensePac Micro Systems, Garden Grove, Calif., USA, Electronics Packaging and Production, p. 24, Nov. 1994;
“First Three-Chip Staked CSP Developed”, Semiconductor International, January 2000, p. 22;
“High-Density Packaging: The Next Interconnect Challenge”, Semiconductor International, February 2000, pp. 91–100;
“3-D IC Packaging”, Semiconductor International, p. 20, May 1998;
“High Density Pixel Detector Module Using Flip Chip and Thin Film Technology” J. Wolf, P. Gerlach, E. Beyne, M. Topper, L. Dietrich, K. H. Becks, N. Wermes, O. Ehrmann and H. Reichl, International System Packaging Symposium, January 1999, San Diego;
“Copper Wafer Bonding”, A. Fan, A. Rahman and R. Rief, Electrochemical and Solid State Letters, 2(10), pp. 534–536, 1999;
“Front-End 3-D Packaging”, J. Baliga, Semiconductor International, December 1999, p 52, are also believed to represent the state of the art.